دانلود رایگان مقاله انگلیسی طراحی فیزیکی غیرقابل قبول مبتنی بر اینورتر بسیار سبک وزن و قابل تنظیم - IEEE 2018

ABSTRACT

A physical unclonable function (PUF) is a promising security primitive which utilizes the manufacturing process variations to generate a unique unclonable digital fingerprint for a chip. It is especially suitable for resource constrained security applications, e.g. internet of things (IoT) devices. The ring oscillator (RO) PUF and the static RAM (SRAM) PUF are two of the most extensively studied PUF designs. However, previous RO PUF designs require a lot of hardware resources for ROs to be robust and SRAM PUFs are not suitable for authentication. The previous research by the author proposed a tristate static RAM (TSRAM) PUF which is a highly flexible challenge response pair (CRP) based SRAM PUF design. In this paper, a novel configurable PUF structure based on tristate inverters, namely a tristate configurable ring oscillator (TCRO) PUF is proposed. A configurable delay unit, composed of a tristate matrix, is used to replace the inverters in the RO PUF. The configurable bits are able to select a subset of the tristate inverters in the delay unit. Each tristate inverter is completely utilized by using the configurable delay unit and thus the approach enhances the flexibility and entropy of the proposed PUF design. The proposed PUF design can generate an exponential number of CRPs compared with the conventional RO PUF. Moreover, the proposed design significantly reduces the hardware resource consumption of the RO PUF. Delay models of both the TSRAM PUF and the proposed TCRO PUF designs are presented. A comprehensive evaluation of the TSRAM PUF is proceeded. To validate the proposed TSRAM PUF and TCRO PUF designs, a simulation based on UMC 65nm technology and a hardware implementation on a Xilinx Virtex-II FPGA are presented. The experimental results demonstrate good uniqueness and reliability as well as high efficiency in terms of hardware cost.

VII. CONCLUSION

In this paper, a novel and efficient TCRO PUF is proposed and a previous proposed TSRAM PUF is evaluated. A tristate inverter gate is utilized to allow dynamic reconfiguration of the basic cell in both the TCRO PUF and TSRAM PUF designs. The TCRO PUF and TSRAM PUF are desirable for low-cost and low-power security applications. The functionality and performance of the TCRO and TSRAM PUF designs are validated by both simulation using UMC 65nm technology and implementation on a Xilinx Virtex II FPGA. The experimental results show that the TSRAM PUF achieves good uniqueness and reliability results, which uniqueness results of 49.7% and 43.4% on ASIC and FPGA respectively, as well as a reliability result of 5.34% over a temperature range of 0 ◦C ∼ 70◦C with 10% fluctuation in supply voltage on FPGA. Furthermore, the TSRAM PUF can provide CRPs that are not available using a conventional SRAM PUF. The TCRO PUF also achieves good uniqueness results of the values of 49.69% and 48.30% on ASIC and FPGA respectively, as well as good reliability results of a value of 4.73% on FPGA. Also, the TSRAM PUF and the proposed TCRO PUF use less hardware resources compared with previous designs, which makes the proposed PUF design very promising in resource-constrained applications.