دانلود رایگان مقاله طراحی و پیاده سازی شمارنده اجزای نرم افزار تعریف شده برای SDN

Abstract

In Software-Defined Networking (SDN), central controllers can obtain global views of dynamic network statistics to manage their networks. In order to support SDN controllers to obtain global information of the networks, the data planes need to maintain a large number of counters, which are typically implemented in hardware such as ASIC. However, implementation of these counters in hardware faces critical challenges: high memory consumption, control inflexibility, and low statistical accuracy. In this paper, we present the concept of Software Defined Hardware Counters (SDHC) for SDN, which offloads the management of counter updating to software and still maintains practical execution efficiency in hardware. Therefore, SDHC can allocate counter memory on demand to enhance counter utilization, which greatly reduces on-chip memory consumption. It is able to allow controllers to flexibly control the counters through south-bound interface. Besides, with novel statistics feedback mechanisms, SDHC supports high-accuracy and active statistical requirement applications. Through a prototype implementation and performance evaluation based on FPGA and general processor, we reveal that the proposed SDHC is able to achieve high processing performance and high statistical accuracy, which incurs negligible updating delay to the switches.

8. Conclusion and future work

Our paper proposes the concept of SDHC, which of- floads management function of updating counters from hardware to software and still maintains practical execution functions in hardware. Through allocating counter memory on demands, it effectively reduces the requirements of on-chip counter memory. By providing the SDHC south-bound interface, SDHC enhances the flexibility of introducing and controlling counters. Meanwhile, active statistical modes bring in high statistical accuracy compared with the traditional passive mode. Therefore, SDHC can meet diverse statistical requirements of applications in SDN. Prototype implementation and evaluation reveal that SDHC has high processing performance and high statistical accuracy, and negligible updating delay. We believe that SDHC is an exciting and promising idea for SDN counters, which accords with the development of SDN that makes network more flexible and manageable. In future work, there are several research directions we intend to pursue to improve SDHC: (1) in order to vastly improve the updating performance, we aim to investigate better ways to parallelize SDHC; (2) we intend to theoretically analyze statistical requirement of some specialized scenarios using mathematical modeling, in order to qualify the practical requirement of un-sematic counter memory; (3) we need to further standardize the interface of SDHC to better promote the development of SDHC-enabled OpenFlow.