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Abstract

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing PMOS transistors at the input of the comparator.

6. Conclusion

A high speed low power comparator is presented. In this circuit, the voltage variation of the first stage is limited to Vdd=2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. Moreover, the speed of the circuit and maximum input common mode range is increased. That is because owing to the higher common mode voltage at the output of the first stage, the delay of the latch stage is reduced. Analytical derivations of the delay verify the high speed benefit of the proposed comparator. Moreover, solid analysis is presented that models the delay of the comparator. Simulation results in equal budget of power consumption and offset voltage as well post layout simulations prove the advantages of the proposed comparator over the state of the art of published works.