8. Conclusions
This paper identifies the strengths and weaknesses, from a pedagogical perspective, of using computer simulation frameworks at labs, and presents a new approach to cover a wide range of studies on real machines, which cannot be handled by simulators in timebounded labs. The proposal, based on the research expertise of the authors, exploits the performance monitoring capability of current processors, which allows the hardware to track many architectural events (e.g., committed instructions, cache misses, issue stalls, etc.). In this paper, we present the methodology, the scheduling framework, and five labs that illustrate the possibilities of the proposed methodology. The examples present distinct ranges of difficulty, and cover topics such as memory hierarchy, hardware prefetching, issue logic, or SMT cores.
We have applied the proposed methodology during the academic year 2016–2017 in two computer architecture courses at the UPV. We found that the proposed approach helps improving the understanding of the theoretical concepts taught at conventional lessons. Furthermore, it really motivates students to continue their education in computer architecture topics. After applying our methodology, three undergraduate students and one postgraduate that followed these courses are currently performing their final degree thesis and master degree thesis, respectively, in our research team. In addition, two PhD students that were working with simulators in their PhD have moved their work to real machines.
Finally, we would like to emphasize that a key goal of this paper is to serve as a guide to other colleagues to design their labs. With this aim, we have made the source code of the scheduling framework available and presented the lab examples in a rather detailed way.
