دانلود رایگان مقاله طراحی قدرت کارآمد SRAM با لاین پمپ شارژ یکپارچه

ABSTRACT

Bit line toggling of SRAM systems in write operations leads to the largest portion of power dissipation. To reduce this amount of power loss and achieve power efficient memory, we propose a new SRAM design that integrates charge pump circuits to harvest and reuse bit line charge. In this work, a power-efficient charge recycling SRAM is designed and implemented in 180 nm CMOS technology. Post-layout simulation demonstrates an 11% of power saving and 3.8% of area overhead, if the bit width of SRAM is chosen as 8. Alternatively, 22% of power reduction is obtained if the bit width of SRAM is extended to 64. Compared with existing charge recycling SRAM schemes, this proposed SRAM is robust to process variation, demonstrates good read/write stability, and illustrates better trade-off between design complexity and power reduction.

6. Conclusion

To the best of our knowledge, it is the first time that an integrated charge pump circuit was proposed to work inside SRAM systems and to recycle bit line charge in memory write operation. Circuit design, analysis and VLSI implementation of an 8 Kb CPSRAM system are presented in this work. Compared to conventional 6T-SRAM design, the proposed system leads to a remarkable power saving of 11% with a negligible area overhead of only 3.8%. In contrast with existing charge recycling SRAM designs, this proposed CP-SRAM design is robust to process variation and demonstrates good read/write stability, as well as better trade-off between design complexity and low power consumption.