I. INTRODUCTION

The increased usage of automated manufacturing and testing equipment has led to environments that are more likely to have the presence of the charge device model (CDM) ESD, rather than the more well-known human body model (HBM). CDM events can easily reach several Amps within 1 ns and are accompanied by damped but fast oscillations, which makes the development of an accurate and compact model for CDM ESD devices very difficult. Silicon controlled rectifier (SCR) has long been used as a robust and area-efficient on-chip ESD protection device, but an SCR compact model for CDM ESD applications is not widely available. Juliano and Rosenbaum developed a model based on the Verilog-A coded behavior modeling to describe the SCR snapback [1], but a smoothing function has to be used to ensure continuity. Other SCR compact models built from a macromodel consisting of existing device models were intended for transmission line pulsing (TLP) or HBM responses and are not applicable for the simulation of circuits subject to the CDM stress [2]-[4]. In this paper, we seek to develop a comprehensive and accurate compact model for a high-holding, lowvoltage triggering SCR (HH-LVTSCR) [5], with special attentions given to accurately modeling the CDM-relevant operation states in order to simulate the response of complete I/O circuits under CDM stresses.