Abstract
A multiplier is the basic structural unit of many arithmetic logical units(ALU), digital signal processing(DSP) and communication system. So the area, speed and power consumption are the prime factors for the designing of multiplier circuits. QCA (Quantum dot-Cellular Automata) is one of the alternatives, which yields small size and low power consumption. In this paper, we proposed a 4-bit Vedic multiplier (using Urdhva Tiryagbhyam sutra) in QCA Technology. The generated partial product addition in Vedic multiplier is realized using carry-save technique. The design is simulated on QCA Designer tool and it confirms the efficiency of the design. The simulation result shows that, the proposed design has reduced 30% cell count, 60% reduction in area and 50% delay as compared to the 4x4 Wallace and Dadda multiplier.
