دانلود رایگان مقاله کاهش تداخل کانال مجاور در سیستم ارتباطی وابسته به وسایط نقلیه

Abstract

In the last few decades, dedicated wireless channels were specifically allocated to enable the development and implementation of vehicular communication systems. The two main protocol stacks, the WAVE standards proposed by the IEEE in the United States and the ETSI ITS-G5 in Europe, reserved 10 MHz wide channels in the 5.9 GHz spectrum band. Despite the exclusive use of these frequencies for vehicular communication purposes, there are still cross channel interference problems that have been widely reported in the literature. In order to mitigate these issues, this paper presents the design of a two-stage FIR low-pass filter, targeting the integration with a digital baseband receiver chain of a custom vehicular communications platform. The filter was tested, evaluated and optimized, with the simulation results proving the effectiveness of the proposed method and the low delay introduced in the overall operation of the receiver chain.

5. Conclusions and future work

In this paper, a two-stage low-pass FIR filter has been proposed with the main goal of mitigating the effects of adjacent channel interference in vehicular communication systems. First, an interpolated FIR filter with a narrow transition band was designed to strongly attenuate the spectral components of the interfering signal close to the desired channel. And then, a polyphase decomposed FIR filter was employed to eliminate the passband replicas of the IFIR filter. The design followed a multi-rate approach, taking advantage of the decimation block in the interface between the analog and the digital domains of the receiver chain. The behavior of this two-stage filter was simulated and tested in MATLABs and the results have shown that the proposed solution significantly reduces the impact of the adjacent channel transmissions in the signal of interest. Furthermore, the cascade of the two filters can be efficiently implemented in an FPGA, consuming simple digital hardware blocks. In addition, only a small delay is introduced in the decoding process of the receiving platform. As future work, the designed filter will be implemented in an FPGA and integrated in the operation of the IT2S platform. This way, it will be possible to evaluate the performance of the proposed solution in a real-world scenario. Metrics such as packet error rates, could be analyzed under the presence of an interfering node, and the statistics could be compared with the present situation, where no filtering operation is involved.