Abstract
Power density and cooling issues are limiting the performance of high performance chip multiprocessors (CMP) and off-chip communications currently consume over 20% of power for memory, coherence, PCI and Ethernet links. Photonic transceivers integrated with CM Ps are being developed to overcome these issues, potentially allowing low hop count switched connections between chips or data center servers. H owever, latency in setting up optical connections is critically important in all computing applications and having transceivers integrated on the processor chip also pushes other network functions and their associated power consumption onto the chip. I n this paper, we propose a low latency optical switch architecture which minimizes power consumed on the processor chip for two scenarios: multiple socket shared memory coherence networks and optical top-of-rack switches for data centers. The switch architecture reduces power consumed on the CM P using a control plane with a simplified send and forget server interface and the use of a hybrid M ach-Zehnder I nterferometer (M ZI) and semiconductor optical amplifier (SOA) integrated optical switch with electronic buffering. Results show that the proposed architecture offers a 42 % reduction in head latency at low loads compared with a conventional scheduled optical switch as well as offering increased performance for streaming and incast traffic patterns. Power dissipated on the server chip is shown to be reduced by over 60% compared with a scheduled optical switch architecture with ring resonator switching.
