ترجمه مقاله نقش ضروری ارتباطات 6G با چشم انداز صنعت 4.0
- مبلغ: ۸۶,۰۰۰ تومان
ترجمه مقاله پایداری توسعه شهری، تعدیل ساختار صنعتی و کارایی کاربری زمین
- مبلغ: ۹۱,۰۰۰ تومان
It is important to find an efficient design-for-testability (DFT) methodology that satisfies both security and testability, although there exists an inherent contradiction between security and testability for digital circuits. Scan design is a powerful DFT technique that provides high controllability and observability over a chip and yields high fault coverage [1]. However, this also accommodates reverse engineering, which damages security. For secure chip designers, there is a demand to protect secret data from sidechannel attacks and other hacking schemes[2]. Different approaches[3]–[9] have been proposed to solve this problem. All the approaches except [7] add extra hardware outside of the scan chain. Disadvantages of this are high area overhead, timing overhead or performance degradation, increased complexity of testing, and limited security for the registers part, among others.